1. Field of the Invention
The present invention relates to a field effect transistor, and in particular to a field effect transistor formed of a compound semiconductor of the GaAs system.
2. Related Background Art
A GaAs field effect transistor (hereinafter referred to as FET) has been researched and developed in various kinds for practical use as a high-frequency element because its carrier has greater saturation velocity and a higher saturation speed.
To allow such elements to be used at a more high-frequency, it is required to increase the transfer conductance (gm) by making the elements finer or by making the channel layer thinner and concurrently to improve gate-source resistance voltage and current driving function, for which various studies have been made and proposed.
For example, in the Japanese Patent Application Laid Open No. 166081/1986 and No. 276270/1986, there has been disclosed a FET having a channel wherein planar dope layers provided with an ionized donor are formed by a planar dope technique. In the Japanese Patent Application Laid Open No. 82677/1989, one form of the channel layer wherein two planar dope layers are provided within the mean free path of electron, is disclosed.
Examples aiming at the function due that GaInAs has greater electron saturation velocity and saturation speed compared with GaAs, are disclosed in the Japanese Patent Application Laid Open No. 272080/1988, No. 2371/31989, and No. 57677/1989. The Japanese Patent Application Laid Open No. 90861/1988 discloses one paying attention that Si has a higher doping efficiency etc. Furthermore, it is well known that, if GaInAs having smaller band gap is provided on GaAs, exudation of carrier to a GaAs buffer layer can be suppressed.
However, even in any of the conventional techniques described above, field effect transistors having satisfactory characteristics have not yet been realized. In the prior art using above planar dope technique, because the planar dope layer is provided between semiconductor layers with larger valence band, the enclosure of carrier might not be sufficiently achieved. In the prior art paying attention to a GaInAs characteristic as above, various drawbacks arise such that an irregularity of the lattice matching at the interface of GaAs and GaInAs increases.
Accordingly, there has yet not been realized a field effect transistor which is superior to terms of saturation velocity, confined efficiency of carrier, and doping efficiency, and making possible any of current driving function, transfer conductance, and gate-source resistance voltage.